Rapid optical metrology of critical dimensions of large-area nanostructure arrays with complex patterns
Background
Scatterometry-based metrology has the capability to perform high-throughput inspection of geometric characteristics of large-area nanopatterned surfaces. It utilizes physics-based dependencies between reflectance of light scattered from nanopatterned surfaces for pre-defined set of wavelengths and Critical Dimensions (CDs) of such nanopatterns.
Current...
|
Reducing amount of helper data in silicon physical unclonable functions (PUFs) via lossy compression
Background
Silicon physical unclonable functions (PUFs) are widely used in emerging hardware security applications, such as device identification, authentication, and cryptographic key generation. PUFs generate unique randomness by exploiting inherent random process variation during fabrication. Among them, static random-access memory (SRAM) PUFs that...
|
Software for signal segmentation and extraction of informative time-domain features
Background
Industrial manufacturing equipment equipped with large numbers of sensors is commonplace in today’s modern manufacturing systems. From Smart Factories using AI and digital twins, along with the proliferation of the Internet of Things (IoT) to improve efficiency and productivity, one common challenge is what to do with the vast amounts...
|
Plasma-free anisotropic wet etching method for III-N micro LEDs
Background
MicroLED technology are the next big display technology delivering stunning picture quality with spectacularly high resolution and brightness. MicroLED brings all the great aspects of OLED technology—self-emissive, perfect blacks, outstanding color, perfect off-angle viewing—while ditching the organic compounds to produce exceedingly...
|
Wafer alignment with AFM metrology
Background
One of the major challenges in nanoscale manufacturing is defect control. Optical inspection is not an option at the nanoscale level due to the diffraction limit of light, and without inspection high scrap rates can occur. One solution to this problem is inline metrology using atomic force microscopes (AFM). Single chip MEMS based AFMs have...
|
Bidirectional DC/AC topologies
BackgroundRecently, more and more power conversion applications, such as PV micro-inverters, battery storage systems, on-board EV chargers, etc., require isolated DC/AC power converters. The markets for these applications are rapidly growing. The conventional two-stage topology solutions have simple control, higher efficiency, and lower cost. However,...
|
Monolithic, unetched BTO strip waveguides
Background
Electro-optic technology relies on the operation of systems/devices through the propagation and interaction of light with various tailored/optically active materials. Typical electro-optical devices are designed to modulate the properties of a light wave (e.g., phase, polarization, amplitude, frequency, direction of propagation) and include...
|
Analog-to-digital converter (ADC) technologies
Background
Dr. Nan Sun and his research group have developed a portfolio of analog to digital converter (ADC) technologies that are available for licensing. Overall, Dr. Sun’s lab develops high-performance analog/mixed-signal circuits and architectures, with research efforts focusing primarily on designing low-power, high-speed, and high-resolution...
|
Variable gain amplifier utilizing positive feedback and time-domain calibration
BackgroundIn discrete-time systems, including ADCs, a voltage amplifier is necessary to increase the signal swing for further processing. Traditional precision amplification techniques, including closed-loop amplifiers, become less viable in nanometer-scale processes due to reduced transistor intrinsic gain. Additionally, these devices generally consume...
|
Through silicon vias (TSV)
Through silicon vias (TSV) is a key enabling element the provides short vertical interconnects in die stacks to improve electrical performance, power consumption, and form factor for 3D integrated devices. The mismatch of thermal expansion coefficients between the copper via and the silicon wafer can induce significant thermal stresses to degrade the...
|