Analog-to-digital converter (ADC) technologies


Dr. Nan Sun and his research group have developed a portfolio of analog to digital converter (ADC) technologies that are available for licensing. Overall, Dr. Sun’s lab develops high-performance analog/mixed-signal circuits and architectures, with research efforts focusing primarily on designing low-power, high-speed, and high-resolution ADCs and digital-to-analog converters (DACs). They investigate a wide range of ADC and DAC architectures, including pipelined, delta-sigma, and successive approximation registrar (SAR). Their expertise lies in digital background calibration techniques and mismatch shaping techniques. Recently, there has been an interest in time-domain (TD) analog signal processing (ASP) techniques using voltage-controlled oscillators. Such a TD-ASP framework suits well with nanometer-scale CMOS technology. Unlike conventional voltage-domain ASP approaches that suffer from reduced power supply voltages and smaller transistor intrinsic gains, TD-ASP takes advantage of the increased transistor speed and timing resolution brought by CMOS scaling. A select list of papers from Dr. Sun and his group have been included for convenience (6723, 7376, 7430, 7476, 7537), but many more are available on Dr. Sun's website.

Invention descriptions

6723: The invention uses a combination of integration and positive feedback regeneration in order to achieve high-speed amplification. Noise and linearity can be traded off for increased speed by adjusting the lengths of the integration and amplification phases. Additionally, the invention overcomes the issues of process sensitivity and inaccurate gain by implementing a time-domain based calibration technique. The total amplification time can be tuned in the background provide a precise gain across PVT variations.

7060: This work proposes a novel power efficient amplifier. By stacking N inverters and splitting the capacitive feedback into N paths, it achieves 2N-time current reuse for a single-channel input. It has only N output branches to combine, thus turning the prior exponential dependence into a mild linear dependence. It greatly reduces the total current and achieves the best-reported NEF to the inventors’ best knowledge. To verify the proposed inverter-stacking amplifier topology, two prototypes are implemented: one with two stacked inverters and the other with 3 stacked inverters.

7376: This paper presents a 13-bit pipelined-SAR ADC with a continuous-time (CT) input stage that is kT/C noise free. Hence, the 1st-stage capacitor size is not bounded by the kT/C limit and can be significantly reduced. Unlike a classic pipelined-SAR ADC, the sampling operation is moved to the second stage. Therefore, the kT/C noise from the second stage is suppressed by the first-stage gain, making possible the use of a small sampling capacitor in the second stage too. In the prototype ADC, the 1st-stage input capacitor is only 120fF (60fF single-ended), which is 25× smaller than 3pF (set by kT/C noise limit) in a classic DT pipelined-SAR ADC of the same resolution. This substantially smaller capacitor size reduces the chip area. Moreover, it greatly relaxes the performance requirement of the ADC input buffer and the reference buffer, leading to significant power saving on the system level.

7430: Inspired by the noise shaping concept in ΔΣ ADCs, this work opens up a new direction to address the interstage gain error. Instead of boosting the open-loop gain of residue amplifier or correcting the interstage gain error with foreground or background calibration, this work proposes an interstage gain error shaping (GES) technique that can substantially suppress the in-band interstage gain error. It does not require extra clock phase, complicated circuitry, incur large power, or area overhead. It works for both closed-loop and open-loop amplification. To prove the proposed concept, a pipelined SAR ADC capable of operating in two working modes, no interstage GES and second-order interstage GES, was created using CMOS technology.

7476: This invention presents an energy-efficient dynamic comparator with a floating inverter amplifier (FIA) based pre-amp. Its inverter-based input stage naturally realizes two-time current reuse. Moreover, the inverter stage is powered by a floating reservoir capacitor that forms an isolated power domain, making the pre-amp operation independent from the input common-mode (CM) voltage. Thus, the comparator performance becomes much less sensitive to the input CM variation. The pre-amp output CM is also kept constant during the amplification process. Hence, the pre-amp gain is no longer limited by the output CM drop and can be much bigger. Furthermore, the reservoir capacitor provides dynamic source degeneration that increases Gm/ID and prevents full discharge of the load capacitor. This invention introduces a dynamic comparator with a novel pre-amplifier. This pre-amplifier uses an inverter-based input pair powered by a floating reservoir capacitor. It realizes both current reuse and dynamic bias, thereby significantly boosting Gm/Id and reducing noise. In addition, the floating reservoir capacitor provides an isolated voltage domain for the pre-amplifier operation so that it greatly reduces the influence of the input common-mode voltage as well as the process corner.

7537: This invention describes a closed-loop dynamic amplifier. The closed-loop amplifiers can ensure accurate gain, but they typically consume large static current. By contrast, dynamic amplifiers consume low power due to their dynamic operation, but they typically can only work in the open loop with ill-defined gain. It is highly desirable to combine their merits; however, there has been very little progress due to the incompatibility of closed-loop configuration and dynamic operation. This work describes a new capacitively-degenerated dynamic amplifier that has an intrinsically robust output common-mode voltage. It obviates the need for a dynamic common-mode feedback circuit. Moreover, this dynamic amplifier can achieve high gain and ensure closed-loop stability. As a result, this is the world’s first high-performance closed-loop dynamic amplifier.