In discrete-time systems, including ADCs, a voltage amplifier is necessary to increase the signal swing for further processing. Traditional precision amplification techniques, including closed-loop amplifiers, become less viable in nanometer-scale processes due to reduced transistor intrinsic gain. Additionally, these devices generally consume static power, which becomes a larger percentage of overall power consumption as dynamic power decreases with further device scaling. Recently, interest has grown in the usage of dynamic amplifiers in discrete-time systems. These amplifiers consume no static power, allowing for increased power efficiency as devices scale. Additionally, these devices are generally constructed in open-loop configurations, which greatly reduce the gain requirements for the amplifier. These dynamic amplifiers suffer from their own limitations, including increased sensitivity to process variation and inaccurate gain.
Researchers at The University of Texas at Austin have developed a technology that uses a combination of integration and positive feedback regeneration in order to achieve high-speed amplification. Noise and linearity can be traded off for increased speed by adjusting the lengths of the integration and amplification phases. Additionally, the invention overcomes the issues of process sensitivity and inaccurate gain by implementing a time-domain based calibration technique. The total amplification time can be tuned in the background provide a precise gain across PVT variations. Traditional precision amplification techniques, including closed-loop amplifiers, become less viable as CMOS devices continue to scale to smaller sizes. In order to achieve the desired closed-loop gain in the presence of process variation, an open-loop gain many times larger than the desired gain is required. Nanometer-scale devices suffer from reduced intrinsic gain, which limits the maximum achievable open-loop gain. This invention overcomes the scaling problem by amplifying in an open-loop configuration, significantly decreasing the required amplifier gain. The open-loop gain can be tuned to its desired value through the use of a digital timing loop. This invention shifts the complexity of achieving a precise gain from the analog domain to the digital domain, where device scaling is beneficial instead of deleterious.
The technology has been in a 130nm CMOS technology. The low frequency Schreier FoM is 172 dB, and the Nyquist Schreier FoM is 171.2 dB. Performance specifications, comparisons, and block diagrams may be found in the published works here and here. The features and benefits of this technology include:
- High-speed discrete-time amplification
- Variable gain by adjusting amplification time
- No DC power consumption
- Positive feedback amplification
- Simple mixed-signal calibration scheme