Background
A successive approximation analog-to-digital converter (ADC) is used to digitize the physical analog signals to logic digital signals. It often requires low noise to achieve high accuracy. Traditionally the low noise is realized by utilizing a large comparator or averaging. Those methods are not desirable, since a large comparator is power-hungry and averaging accuracy is not high.
Technology description
Researchers at The University of Texas at Austin have developed a technique related to power-efficient SNR enhancement technique for SAR ADCs. By accurately estimating the conversion residue, it can suppress both comparator noise and quantization error. Thus, it allows a noisy low-power comparator and a relatively low-resolution DAC to achieve high resolution. The proposed technique has low hardware complexity, requiring no change to the standard ADC operation except for repeating the least-significant-bit comparisons.
Results
A 7 dB increase in measured signal-to-noise ratio with only 2.5 times increased comparator power is achieved. Overall, the ADC achieves an ENOB of 10.5-bit at 100kS/s while consuming only 645nW power from a 0.7V supply. Without the invention, if we choose the brute-force way to reduce comparator noise by increasing its size and power, we would need to increase the comparator power by a factor of twenty-one (21x). The only changes to the standard SAR operations are: 1) the clock generator is modified to repeat the LSB comparison for 17 times and 2) a 5-bit counter is used to count the number of ‘1’s. A prototype of the ADC has been developed in 65nm CMOS architecture with an active area of 0.03 mm2. Further details of the experimental setup may be found in the publication.
Figure 1. The proposed SAR ADC architecture.
Table 1. Comparison of the proposed architecture. The referenced work in the table are: [1] H.-Y. Tai, H.-W. Chen, and H.-S. Chen, “A 3.2fJ/c.-s. 0.35V 10b 100kS/s SAR ADC in 90nm CMOS,” IEEE VLSI Symp., 2012, pp. 92–93., [2] P. Harpe, E. Cantatore, and A. van Roermund, “An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR,” IEEE ISSCC, 2014, pp. 194–195., and [3] P. Harpe, E. Cantatore, and A. van Roermund, “A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step,” IEEE JSSC, vol. 48, pp. 3011–3018, Dec. 2013.
