Background
Complementary metal-oxide-semiconductor (CMOS) devices are being scaled down aggressively in each technology generation to achieve higher integration density. However, the scaling of CMOS devices is approaching its physical limitations. For example, one significant factor limiting CMOS scaling is off-state power consumption. Within digital logic, the sources that contribute to off-state power consumption include junction leakage, gate induced drain leakage, subthreshold channel current, and gate tunnel currents. These become increasingly significant as the dimensions decrease. For instance, when the length of the channel (the channel can be visualized as the “stream” through which charges—e.g., electrons, holes—flow from the source to the drain of the transistor) in the CMOS device becomes so short, on the order of 20 nm, the transistor is unable to be turned off because of undesirable leakage current between the source and the drain. As a result, new materials and device structures are needed to enable further performance improvements.
Technology description
Researchers at The University of Texas at Austin have developed a method for fabricating a vertical III-V nanowire field-effect transistor, which comprises:
- Depositing a first layer of doped III-V semiconductor material on a substrate of III-V semiconductor material
- Depositing a layer of undoped III-V semiconductor material on top of the first layer of doped III-V semiconductor material
- Depositing a second layer of doped III-V semiconductor material on top of the layer of undoped III-V semiconductor material
- Growing a first dielectric layer on top of the second layer of doped III-V semiconductor material
- Depositing self-assembled monolayers of nanospheres on the first dielectric layer
- Forming nanopillars using the nanospheres as a mask and the first dielectric layer as a hard mask to etch the second layer of doped III-V semiconductor material and the layer of undoped III-V semiconductor material using nanosphere lithography
Results
The figure below demonstrates the process; additional details may be found in the published papers here and here.
